The present disclosure relates to a semiconductor memory device, and more particularly to a sense amplifier of a semiconductor memory device.
Semiconductor memory devices, which are used for storage of information, have been advancing toward low costs, miniaturization, and large capacity, in accordance with the technical advances in computer system and electronic communication fields. In particular, the miniaturization of memory chips provides a technical basis for realizing the large capacity.
Generally, a semiconductor memory device such as a DRAM device includes cell blocks each cell block consisting of a number of cells, each cell in turn including one NMOS transistor and one capacitor, and which are connected to word lines and bit lines connected in the form of a matrix.
Hereinafter, operation of such a general DRAM device will be described in brief.
When the DRAM device operates, the bit lines of one bit line pair, which have been precharged with a voltage corresponding to ½ of a core voltage Vcore in a standby mode before the operation of the DRAM device, are transited to respective voltage levels having a minute difference, as they receive data from associated cells. When a sense amplifier operates in this state, the potentials of the bit lines, which have a minute difference, are varied to levels corresponding to the core voltage vcore and a ground voltage Vss, respectively. The data on each bit line amplified in the above-mentioned manner is transferred to a data bus line in response to an output signal from a column decoder.
Meanwhile, when a read command is input after the potentials of the bit lines in each bit line pair, which have a minute difference, have been varied to the core voltage level and ground voltage level, respectively, in accordance with the amplification operation of the sense amplifier, there may be a problem in that an erroneous data inversion occurs as the potential of the bit line lower than the potential of a local input/output line is increased due to a charge sharing between the bit line and the local input/output line. This will be described with reference to FIGS. 1 to 4.
Referring to FIG. 1, a conventional bit line sense amplifier is illustrated. The conventional bit line sense amplifier includes a sensing latch 10 for amplifying a minute signal transferred from a memory cell to bit lines BLT and BLB in accordance with an input active command, an equalizer circuit 30 for precharging the bit lines BLT and BLB in accordance with a precharge command, and column select switches 20 each adapted to connect an associated one of the bit lines BLT and BLB to an associated one of local input/output lines LIOT and LIOB (FIG. 2) when a read/write command is input.
The bit line sense amplifier having the above-mentioned configuration performs an amplification operation in response to an active command when cell data has a logic value of “0”. As a result, the bit line BLT is transited to a ground voltage level, and the bit line BLB is transited to a core voltage (VCORE) level, as shown in FIG. 2. When a read command is subsequently input, each local input/output line (LIOT or LIOB), which has been precharged to the core voltage level, is transited to a floating state. When a selected one of the column select switches 20 is turned on after a certain time, a charge sharing occurs between the associated bit line (BLT or BLB) and the associated local input/output line (LIOT or LIOB).
Generally, the capacitance of the local input/output lines LIO is several times as large as that of the bit lines. For this reason, when a charge sharing occurs between the associated bit line and local input/output line, the potential of the bit line BLT, which has a ground voltage level, is increased, but the potential of the bit line BLB does not vary because both the bit line BLB and the local input/output line LIOB have a core voltage (VCORE) level.
When the level of a supply voltage VDD is increased, the charge sharing occurs more easily because the gate voltage level of each column select switch 20 is increased.
However, when the potential of the bit line BLT is severely increased, an erroneous data inversion occurs. That is, the bit line BLT is transited to the core voltage level, whereas the bit line BLB is transited to the ground level. Such an erroneous data inversion occurs as the NMOS transistor N1, which was in an OFF state, is turned to an ON state due to an increase in gate voltage level, the NMOS transistor N2 is turned off, the PMOS transistor P1 is turned off, and the PMOS transistor P2 is turned on, in this order.
The erroneous data inversion is accelerated when the distance from the column select switch YS to the gate node of the NMOS transistor N1 is reduced, or when the skew between the NMOS transistors N1 and N2 is increased [(for example, when Vth (N1)<Vth (N2)]. FIG. 4 is a circuit diagram illustrating a transistor arrangement of the conventional bit line sense amplifier. In this transistor arrangement, erroneous data inversion may occur easily because the distance between the column select switch YS and the NMOS transistor N1 is short.